USB-FPGA Module 1.15y:
The USB-FPGA Module 1.15y contains four Spartan 6 XC6SLX150 FPGA's, on-board voltage regulators and a USB controller. It is optimized for computations that do not require much bandwidth and RAM. The FPGA Board allows to build large low-cost clusters using standard components.
Schematics (rev. 1, PDF)
The SDK package contains a lot of examples which can be used as starting point for own applications.
More Information are available in the EZ-USB FX2 SDK section.
The following drawing shows the measurements and the location of the of the described elements.
Click on the image for a larger version or download the PDF version.
The EZ-USB FX2 Microcontroller searches for the firmware at the address 0xA2 which is the default address (jumper open).
The main purpose of this jumper is to disable boot-loading from EEPROM. If, for example, the EEPROM was programmed with a corrupt firmware the Microcontroller can be booted with the internal firmware by closing JP1 during powering-on.
JP1 has an unconnected pin which can be used for parking the jumper. The following pictures show all possible jumper positions:
|Rev. 1: JP1 open||Rev. 1: JP1 closed|
|Rev. 2: JP1 open||Rev. 2: JP1 closed|
CON2 is a pluggable terminal. The two outer contacts are GND (-) and the inner contact is the supply voltage (+). This connector is designed for large currents and should therefore be preferred. The terminal block is delivered with the board.
If non-stabilized power supplies are used it must be made sure that the peak voltage is not larger then 16V, see also Power supply selection guide on the Wiki.
Suggestions for the power supply of FPGA clusters are on the FPGA cluster power supplies page on the Wiki.
The high speed configuration mode requires an output Endpoint of the EZ-USB FX2. The Firmware allows to (re-)use an endpoint which is intended for user defined communication. If all Endpoint buffers of the EZ-USB FX2 are required for input Endpoints standard speed (about 1 MByte/s) configuration via Endpoint 0 has to be used.
The CPLD is factory programmed. Re-programming via JTAG is possible. The sources files and jed file can be downloaded here: usb-fpga-1.15-cpld.zip.
The FPGA can be configured either via USB or via JTAG. If the JTAG interface is used for FPGA configuration bit 0-3 of port E (=PROG_B at FPGA's 1-4) must be driven high. This happens automatically if a firmware developed with the SDK is running.
The FPGA JTAG connector CON4 is not installed by default. It is delivered with the board on request.
The clock signal are distributed using the CPLD.
Four Xilence COO-XPNB.F heat sinks are delivered with the board. These heat sinks can be used actively or passively. In passive mode the fan should be removed. The height of the heat sink (without fan) is 35 mm. The height of the fan is 11 mm.
In order to ensure sufficient heat transfer the heat sinks has to be mounted using the push pins and thermal grease.
If a low profile cooling solution is required Titan TTC-CSC03 coolers are recommended.
Click on the images for larger versions.
USB-FPGA Module 1.15y, rev. 2 without heat sinks. This Spartan 6 LX150 (XC6SLX150) Quad-FPGA Board is optimized for cryptographic computations and allows to build low-cost clusters using standard components.
USB-FPGA Module 1.15y, rev. 1 without heat sinks. This Spartan 6 LX150 (XC6SLX150) Quad-FPGA Board is optimized for cryptographic computations and allows to build low-cost clusters using standard components.
USB-FPGA Module 1.15y with installed heat sinks. The heat sinks are delivered with the board. This FPGA Board contains four Spartan 6 LX150 (XC6SLX150) FPGA and is suitable for cryptographic computations such as Bitcoin Mining.