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ZTEX SDK - Default Firmware

For all Series 2 FPGA Boards there is a default firmware with the following features:
  • Uploading Firmware and Bitstream to volatile memory
  • Access to non-volatile memory and loading Firmware and Bitstream to it
  • Default Firmware Interface, see next section

The SDK contains the update utility DefaultUpdater which detects the type of the FPGA Board and updates the correct default firmware.

Default Firmware Interface

This general purpose communication interface consists in these components:
  • Hi speed interface operating at maximum possible data rate of the hardware
  • Low speed communication with SRAM like interface with separate read and write ports and 256 32 Bit registers (e.g. useful to transfer settings)
  • 4 GPIO pins
  • 1 dedicated reset pin
For most applications this interface is sufficient and thus avoids the need of development of firmware. For instance, all examples of the SDK run with default firmware.

The SDK contains HDL modules for the FPGA side and API support for the host software. The compatibility of the interface makes migration between different Series 2 FPGA Boards simple: The host software can be written independently from FPGA Board and changing the FPGA Board usually only requires updating the constraint files.

The block diagram gives an overview about the usage and features of the Default Firmware Interface.

Block diagram of Default Firmware Interface of ZTEX Series 2 FPGA Boards


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