USB-FPGA Module 2.01:
(larger means faster)
|USB-FPGA Module 2.01b
|Sold out. Will not produced anymore due to market situation (lead time of the FPGA is more than 5 years).
|USB-FPGA Module 2.01c
| Sold-off, to the shop
Will not produced anymore due to market situation (lead time of the FPGA is more than 5 years).
All variants are supported by the free ISE Webpack versions.
The following drawing shows the measurements and the location of the components described here.
Click on the image for a larger version or download the PDF version.
USB-FPGA Modules 2.01 have no mounting holes because they are usually plugged onto an application circuit. Alternatively also one of the add-on cards may be used as mounting adapter.
If the application circuit uses the 3.3V output of the FPGA Board, current draw form USB may exceed the USB specification.
|JP2: Power supply via USB
|JP2: Power supply via VIN pins A1 and B1 of the external I/O connector
JP1 is used tp prevent Firmware booting from EEPROM, e.g. if the firmware is corrupt. At booting the EZ-USB FX2 Microcontroller expects the firmware at the I2C address 0xA2 (jumper open) and falls back to an internal firmware if no valid data is found at this address (jumper closed).
JP1 has an unconnected pin which can be used for parking the jumper. The following pictures show all possible jumper positions:
Additional clocks can be connect to the GCLK pins of the I/O connector.
In most cases the on board clock sources are sufficient.
The maximum configuration speed is 6.5 Mbyte/s and is achieved at 26 MHz SPI Bus speed and 2 Bit SPI Bus width (bitgen settings -g ConfigRate:26 -g SPI_buswidth:2). Bitstream can be written to the Flash by the SDK via USB (most comfortable) or via JTAG using the indirect programming method of the Xilinx Tools, see ZTEX Wiki
If Flash is not used (CS signal high) the other three SPI pins (DIN, CLK and DOUT) can be used as GPIO pins.
On USB-FPGA Modules 2.01 all 100 external I/O's are assigned and have a variable I/O voltage. I/O voltage for rows A and B is VCCO_AB and for rows C and D it is VCCO_CD. By default VCCO_AB and VCCO_CD are connected to 3.3V through 0Ω resistors R8 and R9, respectively. Thus, these pins are 3.3V outputs. (This is the standard behaviour for all FPGA Boards of the Series 2.) If another I/O voltage is required, R8 and/or R9 can be unsoldered and VCCO_AB and/or VCCO_CD can be used as voltage input.
USB-FPGA Modules 2.01 have dual entry female pin headers, i.e. user circuits can be connected to both sides. Plugging user PCB's to top side (component side) of the FPGA Board requires non-standard pin headers with long pins. (The pin headers headers which ara available in the Shop can only be used to connect circuits to bottom side).
The pin assignment of USB-FPGA Modules 2.01 and FPGA-Modules 2.00 are equal.
The FPGA can be configured either via USB or via JTAG. JTAG signals are available on the external I/O connector and JTAG headers are installed on most add-on cards.
Click on the images for larger versions.
Top side of USB-FPGA Module 2.01b with Spartan 6 XC6SLX16 FPGA.
Bottom side of USB-FPGA Module 2.01.