Series 2 FPGA Boards
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  USB-FPGA Module 2.01
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  USB-FPGA Module 2.04
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USB-FPGA Module 2.13:
FPGA Board with Artix 7, EZ-USB FX2 and DDR3 SDRAM

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Table of Contents

Block diagram
Functional description
    Common functions of all Series 2 FPGA Boards
    EEPROM address: JP1
    FPGA state: LED1
    Powering, CON3
    Clock resources
    Configuration booster CPLD and Flash
    External I/O connector
    Heat sink
    Battery option

Additional resources

Schematics (PDF)
Source files and jed file for Configuration Booster CPLD
Pin assignment and net list (Gnumeric format, several sheets)
Pin assignment and net list (Excel format, several sheets)
Eagle Library of the I/O connector
I/O trace length
[external Link] Xilinx Artix 7 Family datasheets from the Xilinx homepage
[external Link] Cypress CY7C68013A/14A datasheet from the Cypress homepage
[external Link] EZ-USB FX2 Technical Reference Manual from the Cypress homepage


Debug Board
Series 1 Adapter Board
Cluster base board

ZTEX FPGA Board with Artix 7, DDR3 SDRAM and USB 2.0

Block diagram

Block diagram of the ZTEX FPGA Board with Artix 7, DDR3 SDRAM and USB 2.0


  • USB 2.0 interface with Mini-USB connector (B-type)
  • Cypress CY7C68013A EZ-USB FX2 Microcontroller (100 pin version)
  • Four Xilinx Artix 7 FPGA variants: XC7A35T, XC7A50T, XC7A75T and XC7A100T, see Variants
  • External I/O connector (consisting in two female 2x32 pin headers with 2.54mm grid) provides:
  • 256 MByte DDR3 SDRAM:
    • Up to 400 MHz clock frequency
    • 16 Bit bus width
    • Up to 1600 MByte/s data rate
    • Usable with the Xilinx Memory Interface Generator (MIG), examples are included in the SDK
  • 128 MBit on-board Flash memory
    • Allows Bitstream loading from Flash to FPGA (up to 16.5 MByte/s)
    • Accessible from EZ-USB FX2 and from FPGA, see the CPLD description
  • 128 Kbit EEPROM memory (can be used to store the EZ-USB firmware)
  • 2 Kbit MAC-EEPROM: contains a unique non erasable MAC-address and is used to store firmware settings
  • Fast FPGA configuration via USB using CPLD: up to 24 MByte/s
  • On-Board power supply:
    • 3.3 V: 2000 mA
    • 1.8 V: 1000 mA
    • 1.5 V: 2000 mA
    • 1.0 V: 4000 mA
  • XC7A50T, XC7A75T and XC7A100T variants: Heat sink for high performance / high speed applications, see Section heat sink
  • Optional:
    • Battery to store a key for bitstream encryption
    • On-board JTAG connector


Four variants with different FPGA's are offered:

Variant FPGA Speed grade
(larger means faster)
Temperature range Availability
USB-FPGA Module 2.13a XC7A35T 1C 0-70°C Will be replaced by USB-FPGA Module 2.12b. Remainders in the Shop
USB-FPGA Module 2.13b XC7A50T 1C 0-70°C EOL, to the Shop
USB-FPGA Module 2.13b2 XC7A50T 1I -40-85°C In production, Stock type, to the Shop
USB-FPGA Module 2.13c XC7A75T 2C 0-70°C In production, Stock type, to the Shop
long term availability
USB-FPGA Module 2.13d XC7A100T 2C 0-70°C In production, Stock type, to the Shop

All variants are supported by the free Vivado Webpack versions.

Functional description

The following drawing shows the measurements and the location of the described elements.

Technical drawing of the ZTEX FPGA Board with Artix 7 XC7A35T to XC7A100T, DDR3 SDRAM and USB 2.0
Click on the image for a larger version or download the PDF version.

USB-FPGA Modules 2.13 have no mounting holes because they are usually plugged onto an application circuit. Alternatively also one of the add-on cards may be used as mounting adapter.

Common functions of all Series 2 FPGA Boards

USB-FPGA Modules 2.13 belong to ZTEX FPGA Board Series 2. All functions that are shared with the other members of this Series are described on the Series 2 FPGA Board page

EEPROM address: JP1

Jumper JP1 specifies the I2C address of the EEPROM:

JP1 I2C address
open 0xA2
close 0xAA

JP1 is used tp prevent Firmware booting from EEPROM, e.g. if the firmware is corrupt. At booting the EZ-USB FX2 Microcontroller expects the firmware at the I2C address 0xA2 (jumper open) and falls back to an internal firmware if no valid data is found at this address (jumper closed).

JP1 has an unconnected pin which can be used for parking the jumper. The following pictures show all possible jumper positions:

     ZTEX FPGA Board with Artix 7 XC7A35T to XC7A100T: JP1 open 1 ZTEX FPGA Board with Artix 7 XC7A35T to XC7A100T: JP1 open 2           ZTEX FPGA Board with Artix 7 XC7A35T to XC7A100T: JP1 closed     
JP1 open JP1 closed

FPGA state: LED1

LED1 indicates the configuration state of the FPGA as follows:

on unconfigured
off configured

Power connector: CON3

External power can be supplied via CON3 or pins A1 and B1 of the external I/O connector. CON3 is a standard DC power jack with 2.1mm center pin (+) diameter and 5.5mm barrel (-) diameter for a supply voltage of 4.5 V to 16 V. A1 and B1 of the I/O connector and the center pin of CON3 are connected directly. This allows to supply a base board from the FPGA board.

For most applications (especially if memory if used) USB standard does not guaranty sufficient current in order to power USB-FPGA Modules 2.13. Nevertheless, the FPGA Board can be powered from USB if the optional 0 Ω resistor R102 (package 0805) is installed (bottom side below USB connector, see drawing). In that case care must be taken in order to prevent that no second power external power supply is connected to CON3 or pins A1 and B1 of the external I/O connector.

Clock resources

On the FPGA board two clocks sources are connected to the FPGA: the clock output of the EZ-USB FX2 which is usually configured to 48 MHz and the interface clock which can be configured to 30 MHz or to 48 MHz. They can be used to generate new clocks within the FPGA using MMCM's or PLL's.

Additional clocks can be connect to the MRCC and SRCC pins of the I/O connector. (These pins are arranged as differential pairs, e.g. L12P_T1_MRCC_35 and L12N_T1_MRCC_35. Single ended clocks must be connected to the positive pin, e.g. L12P_T1_MRCC_35.)

In most cases the on board clock sources are sufficient.

Configuration booster CPLD and Flash

The CPLD allows high speed configuration of the FPGA via USB (up to 24 MByte/s). This requires an output Endpoint of the EZ-USB FX2. The Firmware allows to (re-)use an endpoint which is intended for user defined communication. If all Endpoint buffers of the EZ-USB FX2 are required for input Endpoints standard speed (about 1 MByte/s) configuration via Endpoint 0 has to be used.

The CPLD also controls the access of the Flash and FPGA configuration pins shared by different configuration sources. The following table gives an overview about the access and FPGA configuration modes. CM1:CM0 are the configuration mode pins of the CPLD and are driven by FX2. They are pulled up, i.e. default mode at FX2 start-up is 1:1. The mode pins M2:M1:M0 of the FPGA are driven by CPLD.

CM1:CM0 M2:M1:M0 CCLK driven by: Configuration source Flash can be accessed by:
1:1 1:0:1 - JTAG only FX2
1:0 1:1:0 FX2:CTL5 USB (high speed mode, up to 24 MByte/s) or JTAG -
0:1 1:1:0 FX2:PC6 USB (low speed mode, about 1 MByte/s) or JTAG -
0:0 0:0:1 FPGA Flash (up to 16.5 MByte/s) or JTAG FPGA (and FX2 after successful configuration)

This table is just a brief summary because all configuration related issues are automatically handled by the firmware and the factory programmed CPLD. Interested user are referred to the schematics and the CPLD data package usb-fpga-2.13-2.16-cpld.zip which contains the source files and the jed file for programming the CPLD via JTAG.

More information about using the Flash for FPGA configuration can be found on the ZTEX Wiki.

I/O Connector

The external I/O connector is compatible to other FPGA Boards of the Series 2 and therefore described at page of Series 2 FPGA Boards. The pin assignment is the same as for USB-FPGA Modules 2.14. This allows easy migration between these two FPGA-Boards.

On USB-FPGA Modules 2.13 all 100 external I/O's are assigned and have a variable I/O voltage. I/O voltage for rows A and B is VCCO_AB and for rows C and D it is VCCO_CD. By default VCCO_AB and VCCO_CD are connected to 3.3V through 0Ω resistors R8 and R9, respectively. Thus, these pins are 3.3V outputs. (This is the standard behaviour for all FPGA Boards of the Series 2.) If another I/O voltage is required, R8 and/or R9 can be unsoldered and VCCO_AB and/or VCCO_CD can be used as voltage input.

Heat sink

For some applications heat sinks may be required. Variants b to d (XC7A50T, XC7A50T and XC7A100T) are delivered with a heat sink kit consisting in the following components:
  • 1 14×14×10mm passive heat sink
  • 2 double-sided adhesive thermal pads

Safest way to remove these heat sinks is to lift them up at one corner using the blade of a thin knife. Never pull up or lever up the heat sink using a screw driver or similar tool. This may damage the PCB.


The FPGA can be configured either via USB or via JTAG. JTAG signals are available on the external I/O connector and JTAG headers are installed on most add-on cards. Optionally a 14 pin header (CON5) can be installed as depicted on the side. (By default it is not installed for space reasons). The JTAG headers are available in the shop.

The JTAG interface can also be used for re-programming the CPLD.

Battery option

If Bitstream encryption is required a standard 3V Lithium battery with a pin distance of 10×3mm can be installed. Furthermore two 0805 SMD resistors need to be soldered, R100: 5.6 MΩ and R101: 3.3 MΩ. Taking into account the battery degeneration the data retention time should be at least 10 years.

The battery allows the FPGA to store a key which is used for bitstream encryption in a special low-power memory. The key has to be uploaded via JTAG.

In order to prevent damage R100 must be soldered before the battery is installed. Also care should be taken in order to prevent shortcuts that can cause voltage drop and loss of encryption data.

The picture on the side shows an USB-FPGA Module 2.13 with installed battery, R100, R101 and JTAG header CON5. FPGA Boards with factory-installed battery components and/or JTAG are available on request.

Instructions for Bitstream encryption can be found on the Wiki.

ZTEX USB-FPGA Module 2.13 with JTAG and battery for bitstream encryption


Click on the images for larger versions.

Top side of the ZTEX FPGA Board with Artix 7 XC7A100T, DDR3 SDRAM and USB 2.0

Top side of USB-FPGA Module 2.13d with Artix 7 FPGA XC7A100T.

Bottom side of the ZTEX FPGA Board with Artix 7 XC7A35T to XC7A100T, DDR3 SDRAM and USB 2.0

Bottom side of USB-FPGA Module 2.13.

ZTEX FPGA Board with Artix 7 XC7A35T to XC7A100T, DDR3 SDRAM and USB 2.0: heat sink installed

USB-FPGA Module 2.13 with installed heat sink.

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