USB-FPGA Module 2.14:
Artix 7 FPGA Board with EZ-USB FX3S USB 3.0 controller and DDR3 SDRAM.
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Block diagram
Schematics (PDF) |
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Xilinx Artix 7 Family datasheets from the Xilinx homepageBlock diagram
Features
- USB 3.0 interface with Micro-USB connector
- Cypress CYUSB3033 EZ-USB FX3S Microcontroller:
- ARM926EJ core at 208 MHz
- 512 KByte SRAM
- 1 Storage Port
- 16 Bit GPIF II at 104 MHz (bandwidth between EZ-USB FX3S and FPGA: 204 MByte/s)
- Five Xilinx Artix 7 FPGA variants: XC7A15T, XC7A35T, XC7A50T, XC7A75T and XC7A100T, see Variants
- External I/O connector (consisting in two female 2x32 pin headers with 2.54mm grid) provides:
- 100 General Purpose I/O's (GPIO) connected to FPGA
- JTAG signals
- Reset signal
- External power (6 V .. 16 V) input
- 3.3V output
- I/O voltage output or input, see External I/O connector
- Same pin assignment as USB-FPGA Module 2.13 and USB-FPGA Module 2.14
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256 MByte DDR3 SDRAM:
- Up to 400 MHz clock frequency
- 16 Bit bus width
- Up to 1600 MByte/s data rate
- Usable with the Xilinx Memory Interface Generator (MIG), examples are included in the SDK
- 128 MBit on-board Flash memory
- Allows storage and auto-boot of Firmware
- Allows storage and auto-boot of Bitstream
- Accessible from EZ-USB FX3S and from FPGA, see the CPLD description
- SD card socket
- SD 3.0 (SDXC) support
- SDIO 3.0 support
- 2 Kbit MAC-EEPROM: contains a unique non erasable MAC-address and is used to store firmware settings
- On-Board power supply:
- Two reverse current protected supply inputs: External power (6 V .. 16 V) and USB power
- 5.0 V: 250 mA
- 3.3 V: 3000 mA
- 1.8 V: 1500 mA
- 1.5 V: 1500 mA
- 1.2 V: 1500 mA
- 1.0 V: 4000 mA
- OTG supply switchable and reverse current protected
- XC7A50T, XC7A75T and XC7A100T variants: Heat sink for high performance / high speed applications, see Section heat sink
- Optional:
- Battery to store a key for bitstream encryption
Variants
Five variants with different FPGA's are offered:
| Variant | FPGA | Speed grade (larger means faster) |
Temperature range | Availability |
| USB-FPGA Module 2.14a | XC7A15T | 1C | 0-70°C | On request |
| USB-FPGA Module 2.14b | XC7A35T | 1C | 0-70°C | In production, Stock type, to the Shop |
| USB-FPGA Module 2.14c | XC7A50T | 1C | 0-70°C | EOL, Stock type, to the Shop |
| USB-FPGA Module 2.14c2 | XC7A50T | 1I | -40-85°C | In production, Stock type, to the Shop |
| USB-FPGA Module 2.14d | XC7A75T | 2C | 0-70°C | In production, Stock type, to the Shop |
| USB-FPGA Module 2.14e | XC7A100T | 2C | 0-70°C | In production, Stock type, to the Shop |
All variants are supported by the free Vivado Webpack versions and the ZTEX SDK.
Functional description
The following drawing shows the measurements and the location of the described elements.
Click on the image for a larger version or download the PDF version.
USB-FPGA Modules 2.14 have no mounting holes because they are usually plugged onto an application circuit. Alternatively also one of the add-on cards may be used as mounting adapter.
Common functions of all Series 2 FPGA Boards
USB-FPGA Modules 2.14 belong to ZTEX FPGA Board Series 2. All functions that are shared with the other members of this Series are described on the Series 2 FPGA Board pageJP1
Jumper JP1 is used to disable loading Firmware from Flash during start-up, see Firmware loading. JP1 has an unconnected pin which can be used for parking the jumper. The following pictures show all possible jumper positions:
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| JP1 open | JP1 closed |
Internals about the mechanism of disabling Flash can be found in the CPLD description.
LED1, LED2
LED1 is a duo-LED which is connected to the FPGA. The single LED2 is connected to the EZ-USB FX3. Functions are listed in the following table:| LED1, short wavelength | FPGA configuration state: on if unconfigured |
| LED1, long wavelength | User defined: connected to FPGA pin T11, output is inverted |
| LED2 |
User defined: connected to GPIO53 of EZ-USB FX3 (Firmware: ZTEX_GPIO_LED) Default Firmware: on if USB is connected |
Powering, CON3
USB-FPGA Modules 2.14 can be powered from USB or externally. Both inputs are protected by a diode, i.e. power sources can be changed during runtime and both inputs can be driven at the same time. For this reason, if the FPGA Board is to be powered externally the voltage must be larger than the USB voltage, i.e. typically at least 6V.Whether USB delivers sufficient current depends on the application and the USB type. Usually applications that use the DDR3 SDRAM can't be driven from USB 2.0 and applications that fully utilize the larger FPGA's need external supply.
External power can be supplied via CON3 or pins A1 and B1 of the external I/O connector. CON3 is a standard DC power jack with 2.1mm center pin (+) diameter and 5.5mm barrel (-) diameter. Valid supply voltage is 6 V to 16 V. A1 and B1 of the I/O connector and the center pin of CON3 are connected directly. This allows to supply a base board from the FPGA board.
SD card
USB-FPGA Modules 2.14 have a SD card socket which is connected to S-Port 0 of the FX3. The SDK supports SD cards as secondary Flash device. The implementation of this feature should be considered as a demo. In order to make use from the full feature set (SDIO, higher speeds, file system support) the Cypress SDK has to be used.External I/O Connector
The external I/O connector is compatible to other FPGA Boards of the Series 2 and therefore described at page of Series 2 FPGA Boards. The pin assignment is the same as for USB-FPGA Modules 2.13. This allows easy migration between these two FPGA-Boards.On USB-FPGA Modules 2.14 all 100 external I/O's are assigned and have a variable I/O voltage. I/O voltage for rows A and B is VCCO_AB and for rows C and D it is VCCO_CD. By default VCCO_AB and VCCO_CD are connected to 3.3V through 0Ω resistors R8 and R9, respectively. Thus, these pins are 3.3V outputs. (This is the standard behaviour for all FPGA Boards of the Series 2.) If another I/O voltage is required, R8 and/or R9 can be unsoldered and VCCO_AB and/or VCCO_CD can be used as voltage input.
Clock resources
On the FPGA Board two clocks sources are connected to the FPGA, a 26 MHz signal and the interface clock which can be configured. If default firmware is used, frequency of the interface clock is 104 MHz.Additional clocks can be connect to the MRCC and SRCC pins of the I/O connector. (These pins are arranged as differential pairs, e.g. L12P_T1_MRCC_35 and L12N_T1_MRCC_35. Single ended clocks must be connected to the positive pin, e.g. L12P_T1_MRCC_35.)
In most cases the on board clock sources are sufficient. It's recommended to derive internal clocks from the fixed 26 MHz clock.
Board Management CPLD
The CPLD provides several board management functions:- FX3 reset controller: delayed deassertion of reset signal
- FPGA reset controller: asserted by FX3 or by global reset signal
- SPI Switch: see below
- Flash disabling: using JP1 or by FX3, see below
- Clock duplication (in order to assure signal quality)
- Disabling Flash
- Soft reset EZ-USB FX3
- EZ-USB FX3 restarts with internal firmware and waits for being reprogrammed via USB
- Writing new Firmware to FX3 via USB and starting the firmware
| Input | Output | |||
| M0:M1 | JP1 | Current state | Next state | SPI: Master → Slave |
| 0:0 | * | * | S1 | FX3 → FPGA |
| 1:0 | * | * | S2 | FPGA → Flash |
| *:1 | open | start,S3,S4 | S3 | FX3 → Flash |
| *:1 | closed | start,S3,S4 | S4 | disabled |
| *:1 | * | S1,S5 | S5 | FX3 → Flash |
| *:1 | * | S2,S6 | S6 | disabled |
CPLD is controlled by the firmware, i.e. users not need to take care about the CPLD internals mentioned above.
Source files can be found in CPLD package. The CPLD is factory programmed.
Heat sink
For some applications heat sinks may be required. Variants c to e (XC7A50T, XC7A50T and XC7A100T) are delivered with a heat sink kit consisting in the following components:- 1 14×14×10mm passive heat sink
- 2 double-sided adhesive thermal pads
Safest way to remove these heat sinks is to lift them up at one corner using the blade of a thin knife. Never pull up or lever up the heat sink using a screw driver or similar tool. This may damage the PCB.
JTAG
The FPGA can be configured either via USB or via JTAG. JTAG signals are available on the external I/O connector. JTAG headers are installed on most add-on cards.The JTAG interface can also be used for re-programming the CPLD.
Battery option
If Bitstream encryption is required a standard 3V Lithium battery with a pin distance of 10×3mm can be installed. Furthermore two 0805 SMD resistors need to be soldered, R100: 5.6 MΩ and R101: 3.3 MΩ. Taking into account the battery degeneration the data retention time should be at least 10 years.The battery allows the FPGA to store a key which is used for bitstream encryption in a special low-power memory. The key has to be uploaded via JTAG.
In order to prevent damage R100 must be soldered before the battery is installed. Also care should be taken in order to prevent shortcuts at the battery that can cause voltage drop and loss of encryption data.
The picture at the end of this page shows an USB-FPGA Module 2.14 with installed battery, R100 and R101 which is plugged on a Debug Board containing a JTAG header.
FPGA Boards with factory-installed battery components are available on request.
Instructions for Bitstream encryption can be found on the Wiki.
Images
Click on the images for larger versions.
Top side of the ZTEX USB-FPGA Module 2.14 with Artix 7, DDR3 SDRAM and EZ-USB FX3 USB 3.0 controller |
Bottom side of the ZTEX USB-FPGA Module 2.14. |
ZTEX USB-FPGA Module 2.14 with heat sink and battery option on a ZTEX Debug Board |
