USB-FPGA Module 2.04:
(larger means faster)
|USB-FPGA Module 2.04a||XC6SLX16||2||On request (no stock type)|
|USB-FPGA Module 2.04b||XC6SLX16||2||Stock type, to the shop|
|USB-FPGA Module 2.04c||XC6SLX25||3||On request (no stock type)|
All variants are supported by the free ISE Webpack versions.
The following drawing shows the measurements and the location of the components described here.
Click on the image for a larger version or download the PDF version.
USB-FPGA Modules 2.04 have no mounting holes because they are usually plugged onto an application circuit. Alternatively also one of the add-on cards may be used as mounting adapter.
JP1 is used tp prevent Firmware booting from EEPROM, e.g. if the firmware is corrupt. At booting the EZ-USB FX2 Microcontroller expects the firmware at the I2C address 0xA2 (jumper open) and falls back to an internal firmware if no valid data is found at this address (jumper closed).
JP1 has an unconnected pin which can be used for parking the jumper. The following pictures show all possible jumper positions:
|JP1 open||JP1 closed|
CON3 is a standard DC power jack with 2.1mm center pin (+) diameter and 5.5mm barrel (-) diameter for a supply voltage of 4.5 V to 16 V.
For applications that use the memory at full speed USB standard does not guaranty sufficient current in order to power USB-FPGA Modules 2.04. Nevertheless, the FPGA Board can be powered from USB if the optional 0 Ω resistor R100 (package 0805) is installed (bottom side below USB connector, see drawing). In that case care must be taken in order to prevent that no second power external power supply is connected to CON3 or pins A1 and B1 of the external I/O connector.
Additional clocks can be connect to the GCLK pins of the I/O connector.
In most cases the on board clock sources are sufficient.
The maximum configuration speed is 6.5 Mbyte/s and is achieved at 26 MHz SPI Bus speed and 2 Bit SPI Bus width (bitgen settings -g ConfigRate:26 -g SPI_buswidth:2). Bitstream can be written to the Flash by the SDK via USB (most comfortable) or via JTAG using the indirect programming method of the Xilinx Tools, see ZTEX Wiki
If Flash is not used (CS signal high) the other three SPI pins (DIN, CLK and DOUT) can be used as GPIO pins.
On USB-FPGA Modules 2.04 only 88 (of 100) pins from the I/O connector are assigned to FPGA. The remaining 12 pins are connected to Port E (6 pins) and to SIO signals (6 pins) of the EZ-USB FX2 microcontroller.
40 FPGA GPIO pins at rows A and B have the variable I/O voltage VCCO_AB, I/O voltage of remaining pins is fixed to 3.3V. By default VCCO_AB is connected to 3.3V through the 0Ω resistor R8 and is therefore a 3.3V output. (This is the standard behaviour for all FPGA Boards of the Series 2.) If another I/O voltage is required, R8 has to be unsoldered and VCCO_AB is used as voltage input. (The VCCO_CD pins of the I/O connector are permanently connected to 3.3V.)
The FPGA can be configured either via USB or via JTAG. JTAG signals are available on the external I/O connector and JTAG headers are installed on most add-on cards.
Click on the images for larger versions.
Top side of USB-FPGA Module 2.04b with Spartan 6 XC6SLX16.
Bottom side of USB-FPGA Module 2.04.