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To the shop The Cluster Base Board connects four Series 2 FPGA Boards to a small cluster node. Features 10 bit bus connected to all FPGA Boards and the external I/O connectors 44 bit open ring network for board to board communication. First and last FPGA Board are connected to an external I/O connector. Two 2x32 pin headers for external I/O. Each one contains: 10 bit bus signals 44 GPIO's connected to first or last FPGA Board Power supply pins Additional resources Schematics (PDF) Measurements (PDF)

Functional description

External I/O connectors are named CON1 and CON6. Their pin assignment if listed in the table below. Positions of the components which are de described here can be found in the measurements file.

Net list

Each row in the header of the table below lists components that are connected together. The rows in the table body shows which pins of the parts are connected together.

Here are a few examples how the table is read:

• B8 of CON1 is connected to B6 of FPGA Board 0
• B8 of CON6 is connected to D6 of FPGA Board 3
• B6 of Board 1 is connected to D6 of Board 0
• BUS[0] is connected to A3 of CON1/CON6 and to B3 of Boards 0-3

Board ID pins

The pins D3 and A3 of each FPGA Board are used as board ID as follows:

Z means that the pin is floating. In order to read the ID out the pins have to be internally pulled up (using the PULLUP constraint).

External Power Supply

The VIN pins of the two external I/O connectors and all FPGA Boards are connected to a bus. This means that all FPGA Boards must be driven by the same power supply. But this also allows to supply the cluster node centrally either by using the pluggable terminal CON7 or by using the DC connector of one of the FPGA Boards. The usage of CON7 is recommended because this connector is designed for large currents. The terminal block is delivered with the Cluster Base Board and has three contacts. The two outer ones are GND (-) and the central one is the supply voltage (+).

JTAG headers

Four standard 14 pin JTAG headers are installed. Each one is connected to the FPGA Board which is next to it.

I/O voltages

The 0 Ω resistors R1 to R3 (1206 packages) can be installed if some of the FPGA boards have I/O voltage pins that are configured as inputs. By default all of them are outputs and therefore R1 to R3 should be open. See the schematics and the FPGA Board description for details.

Pins A31 and B31 of the external I/O connector CON1 are connected to VCCO_AB of the first FPGA Board and A31 and B31 of CON6 are connected to VCCO_CD of the last FPGA Board. By default these pins are 3.3V outputs. If another I/O voltage than 3.3V is desired the 0 Ω resistor on the FPGA Board which connects VCCO_AB or VCCO_CD with 3.3V has to be removed and the I/O voltage has to be supplied through pins A31 and B31 of CON1 or CON6, respectively. See the FPGA Board description for details.

Reset: JP1

Closing jumper JP1 hard-resets all FPGA Boards.

Images

Click on the images for larger versions.

Cluster Base Board for four ZTEX Series 2 FPGA Boards