USB-FPGA Module 1.15x:
The USB-FPGA Module 1.15x is a special variant of the USB-FPGA Module 1.15. It contains an on-board power supply and is optimized for computations that do not require much bandwidth and RAM. The FPGA Board can be used for building large low-cost clusters using standard components.
The SDK package contains a lot of examples which can be used as starting point for own applications.
More Information are available in the EZ-USB FX2 SDK section.
Additional documentation including Tutorials can also be found on the ZTEX Wiki
The following drawing shows the measurements and the location of the of the described elements.
Click on the image for a larger version or download the PDF version.
The EZ-USB FX2 Microcontroller searches for the firmware at the address 0xA2 which is the default address (jumper open).
The main purpose of this jumper is to disable EEPROM boot-loading. If, for example, the EEPROM was programmed with a corrupt firmware the Microcontroller can be booted with the internal firmware by closing JP1 during powering-on the FPGA Board.
JP1 has an unconnected pin which can be used for parking the jumper. The following pictures show all possible jumper positions:
|JP1 open||JP1 closed|
Two suggestions for the power supply of FPGA clusters are on the FPGA cluster power supplies page on the Wiki.
Alternatively LED's can be installed on the GPIO connectors, see images below. These LED's may be very helpful for debugging during the development process. A Debug Kit with all necessary parts is available. The following picture shows an installation plan of the parts (also see images for a FPGA board with installed LED's):
The FPGA can be configured either via USB or via JTAG. If the JTAG interface is used for FPGA configuration bit 1 of port A (=PROG_B at FPGA) must be driven high. This happens automatically if a firmware developed with the SDK is running.
The JTAG connector is not installed by default. It is a part of the Debug Kit.
A Xilence COO-XPNB.F heat sink is delivered with the board. This heat sink can be used actively or passively. In passive mode the fan should be removed. The height of the heat sink (without fan) is 35 mm. The height of the fan is 11 mm.
In order to ensure sufficient heat transfer the heat sink has to be mounted using the push pins and thermal grease.
If a low profile cooling solution is required the Titan TTC-CSC03 cooler is recommended.
A List of Connections can be downloaded in Gnumeric and Excel format.
Click on the images for larger versions.
USB-FPGA Module 1.15x without heat sink. This Spartan 6 LX150 (XC6SLX150) FPGA Board is optimized for cryptographic computations and allows to build low-cost clusters using standard components.
USB-FPGA Module 1.15x with installed heat sink. The heat sink is delivered with the board. This FPGA Board contains a Spartan 6 LX150 (XC6SLX150) FPGA and is suitable for cryptographic computations such as Bitcoin Mining.
USB-FPGA Module 1.15x with installed Debug Kit.