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Series 1 FPGA Boards are deprecated. Please switch to Series 2.

The old product page is still available here for documentation purposes.

Table of Contents Features Functional description     Programming of the ATxmega and Examples     External power: CON1 and CON8     JTAG connector: CON3, JP1 and JP2     AVR PDI connector: CON9     LED's     Experimental Board I/O Connector Images Additional resources Schematics (PDF) Eagle Library of the I/O connectors

Features

• Baseboard for USB-FPGA Modules 1.2 and 1.11
• High-efficiency switching regulators to generate the supply voltages
  • 1.2 V @ 2.7 A
  • 2.6 V @ 2.5 A
  • 3.3 V @ 2.5 A
  • Wide input range: 4.5 to 16 V
• AVR ATXmega128A1 microcontroller for analog capabilities:
  • 2 eight-channel, 12 Bit, 2 Msps Analog to Digital Converter (ADC), software selectable gain of up to 64
  • 2 two-channel, 12 Bit, 1 Msps Digital to Analog Converter (DAC)
  • 4 Analog Comparators (AC) with Window-Function and input form DAC
  • DMA controller for data transfers without CPU intervention
  • Firmware programming and NVM access via USB using the EZ-USB FX2 SDK (no programming cables required)
  • 128 KByte Flash + 2 KByte EEPROM
• Up to 76 General Purpose I/O's (GPIO's):

  	USB-FPGA Module 1.2	USB-FPGA Module 1.11
  FPGA GPIO's (3.3 V)	31	49
  XMEGA GPIO's (3.3 V)	27	27
  Special I/O's	9 (I2C, two serial ports, interrupts)	6 (I2C, serial port, interrupts)

• I/O Ports available on a standard 2.54 mm (0.1 inch) grid via four 1x23 pin connectors to which Expansion Boards or Breadboards can be connected
• JTAG interface for the FPGA
• AVR PDI interface for the XMEGA microcontroller
• 12 LED's

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Functional description

The following drawing shows the measurements and the location of the of the described elements.

Click on the image for a larger version or download the PDF version.

Programming of the ATxmega and Examples

External power: CON1 and CON8

Alternatively CON8 can be used to connect non standard power cables. The ground pin of CON8 (quadratic pad) is marked with "B" and the supply pin (oval pad) is marked with "R", see the images below.

JTAG connector: CON3, JP1 and JP2

The voltage for the I/O signals (TCK,TMS,TDI,TDO) is 2.6V. Pin 2 can be used as supply for these signals. Pin 1 (+3.3V) can be used as supply for the JTAG adapter.

On USB-FPGA Modules 1.2 jumpers JP1 and JP2 can be closed to enforce JTAG configuration mode. But usually this is not required since the JTAG interface is always enabled. On USB-FPGA Modules 1.11 these jumpers have no function.

An appropriate power connector set for CON3 is delivered with the Experimental Board.

AVR PDI header

LED's

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Analog Experimental Board I/O Connector

Four 1x23 pin connectors deliver I/O signals and voltages to user circuits.

The drawing shows the position of the connectors.

The Pinlist and the List of Connections are can be downloaded in Gnumeric or Excel format. The following table is is a short version the these files:

[TOC]

Images

Click on the images for larger versions.

Analog Experimental Board 1.10.

Analog Experimental Board with Spartan 6 USB-FPGA Module 1.11 and two Expansion Boards. The depicted set consists in: 1 × Spartan 6 USB-FPGA Module 1.11 (with pin headers) 1 × Analog Experimental Board 1.10 2 × Expansion Board 4 × 1x23 pin female pin header 4 × 1x23 pin male pin header

Analog Experimental Board with Spartan 6 USB-FPGA Module 1.11 and two Breadboards. The depicted set consists in: 1 × Spartan 6 USB-FPGA Module 1.11 (with pin headers) 1 × Analog Experimental Board 1.10 2 × Breadboard 4 × 1x23 pin male pin header