USB-FPGA Module 2.13:
(larger means faster)
|USB-FPGA Module 2.13a||XC7A35T||1||Stock type, to the Shop|
|USB-FPGA Module 2.13b||XC7A50T||1||Stock type, to the Shop|
|USB-FPGA Module 2.13c||XC7A75T||2||Stock type, to the Shop|
|USB-FPGA Module 2.13d||XC7A100T||2||Stock type, to the Shop|
All variants are supported by the free Vivado Webpack versions.
The following drawing shows the measurements and the location of the of the described elements.
Click on the image for a larger version or download the PDF version.
USB-FPGA Modules 2.13 have no mounting holes because they are usually plugged onto an application circuit. Alternatively also one of the add-on cards may be used as mounting adapter.
JP1 is used tp prevent Firmware booting from EEPROM, e.g. if the firmware is corrupt. At booting the EZ-USB FX2 Microcontroller expects the firmware at the I2C address 0xA2 (jumper open) and falls back to an internal firmware if no valid data is found at this address (jumper closed).
JP1 has an unconnected pin which can be used for parking the jumper. The following pictures show all possible jumper positions:
|JP1 open||JP1 closed|
CON3 is a standard DC power jack with 2.1mm center pin (+) diameter and 5.5mm barrel (-) diameter for a supply voltage of 4.5 V to 16 V.
For most applications (especially if memory if used) USB standard does not guaranty sufficient current in order to power USB-FPGA Modules 2.13. Nevertheless, the FPGA Board can be powered from USB if the optional 0 Ω resistor R102 (package 0805) is installed (bottom side below USB connector, see drawing). In that case care must be taken in order to prevent that no second power external power supply is connected to CON3 or pins A1 and B1 of the external I/O connector.
Additional clocks can be connect to the MRCC and SRCC pins of the I/O connector. (These pins are arranged as differential pairs, e.g. L12P_T1_MRCC_35 and L12P_T1_MRCC_35. Single ended clocks must be connected to the positive pin, e.g. L12P_T1_MRCC_35.)
In most cases the on board clock sources are sufficient.
The CPLD also controls the access of the Flash and FPGA configuration pins shared by different configuration sources. The following table gives an overview about the access and FPGA configuration modes. CM1:CM0 are the configuration mode pins of the CPLD and are driven by FX2. They are pulled up, i.e. default mode at FX2 start-up is 1:1. The mode pins M2:M1:M0 of the FPGA are driven by CPLD.
|CM1:CM0||M2:M1:M0||CCLK driven by:||Configuration source||Flash can be accessed by:|
|1:0||1:1:0||FX2:CTL5||USB (high speed mode, up to 24 MByte/s) or JTAG||-|
|0:1||1:1:0||FX2:PC6||USB (low speed mode, about 1 MByte/s) or JTAG||-|
|0:0||0:0:1||FPGA||Flash (up to 16.5 MByte/s) or JTAG||FPGA (and FX2 after successful configuration)|
This table is just a brief summary because all configuration related issues are automatically handled by the firmware and the factory programmed CPLD. Interested user are referred to the schematics and the CPLD data package usb-fpga-2.13-2.16-cpld.zip which contains the source files and the jed file for programming the CPLD via JTAG.
More information about using the Flash for FPGA configuration can be found on the ZTEX Wiki.
On USB-FPGA Modules 2.13 all 100 external I/O's are assigned and have a variable I/O voltage. I/O voltage for rows A and B is VCCO_AB and for rows C and D it is VCCO_CD. By default VCCO_AB and VCCO_CD are connected to 3.3V through 0Ω resistors R8 and R9, respectively. Thus, these pins are 3.3V outputs. (This is the standard behaviour for all FPGA Boards of the Series 2.) If another I/O voltage is required, R8 and/or R9 can be unsoldered and VCCO_AB and/or VCCO_CD can be used as voltage input.
Safest way to remove these heat sinks is to lift them up at one corner using the blade of a thin knife. Never pull up or lever up the heat sink using a screw driver or similar tool. This may damage the PCB.
The FPGA can be configured either via USB or via JTAG. JTAG signals are available on the external I/O connector and JTAG headers are installed on most add-on cards. Optionally a 14 pin header (CON5) can be installed as depicted on the side. (By default it is not installed for space reasons). The JTAG headers are available in the shop.
The JTAG interface can also be used for re-programming the CPLD.
Battery optionIf Bitstream encryption is required a standard 3V Lithium battery with a pin distance of 10×3mm can be installed. Furthermore two 0805 SMD resistors need to be soldered, R100: 5.6 MΩ and R101: 3.3 MΩ. Taking into account the battery degeneration the data retention time should be at least 10 years.
The battery allows the FPGA to store a key which is used for bitstream encryption in a special low-power memory. The key has to be uploaded via JTAG.
In order to prevent damage R100 must be soldered before the battery is installed. Also care should be taken in order to prevent shortcuts that can cause voltage drop and loss of encryption data.
The picture on the side shows an USB-FPGA Module 2.13 with installed battery, R100, R101 and JTAG header CON5. FPGA Boards with factory-installed battery components and/or JTAG are available on request.
Instructions for Bitstream encryption can be found on the Wiki.
Click on the images for larger versions.
Top side of USB-FPGA Module 2.13d with Artix 7 FPGA XC7A100T.
Bottom side of USB-FPGA Module 2.13.
USB-FPGA Module 2.13 with installed heat sink.